This invention generally relates to network processing; more particularly, the invention aims at providing a connection of a network processor packet parser to an external coprocessor for efficiently merging parser and external coprocessor results.
High performance network processors on one chip may have to handle sophisticated network functions. Particularly, a packet parser, for instance in an Ethernet adapter, may have to support high level packet classification and packet filtering functions which cannot be all handled on a chip. In these circumstances, the parser will have to kick-off some packet processing functions to an external coprocessor and get in return the response from the coprocessor in order to use this result as a complement to its own packet process result.
It is common to decide for externalizing network processing functions from the packet parser because different functions may require different processing architecture and performance, the network processor chip being not able to include all these characteristics. The other good reason is an area limitation problem on the chip as packet parsing additional network function may require logic and arrays which may be very large.
A typical additional network processing function which may be externalized by the packet parser to the coprocessor is packet classification including, as an example, a lookup in a ternary content addressable memory (TCAM) or a hash-based lookup for which different search algorithm are employed (Patricia tree, Cuckoo algorithm etc.). One other function which can be externalized by the packet parser to the coprocessor is the packet filtering functions which are based on recognition of patterns extracted from the packet.
Merging in the network processor of results from parser and results coming from the external coprocessor when processing data packets received from the network by the network processor will require two functions: synchronization of the results between the two processing entities (parser and coprocessor) and error handling in case of lost or corrupted results which may come for instance from a failure of synchronization. With 10 Gpbs Ethernet ports, it is necessary to merge the results in the network processor as quickly as every 67.2 ns as shortest Ethernet packets are received every 67.2 ns. A second strong constraint of the implementation is to limit the silicon area: merging process requires traditionally additional first-in-first-out queues (FIFOs) which represent costly memory array (static random access memories (SRAMs) for instance). Synchronization requires, with standard solutions, feedback logic to control reception of results from the external coprocessor. Error handling function includes costly additional data exchange in the Network processor and external coprocessor interface while remaining reasonable. Finally, this process of merging results must be compatible with cases where there is no need of result merging, when the parser processes the data packet itself without having sent a request to the external coprocessor for additional processing.
Due to the use of high-speed serialized lines between the network processor and the external coprocessor, which is the best way to save lines and pins, this solution is more sensitive to errors than the slow speed parallel lines. There is thus a need when implementing such a merging function to have a careful error handling while not too costly in terms of silicon area.
The U.S. Pat. No. 7,428,618 relates to a network node structure architected around two Net Processors, one for each direction of packet streams, communicating through a shared memory. The structure is complemented with a set of coprocessors located on a daughter card. All coprocessors are interconnected via a hardware Control Logic which also provides an interface to one of the two Net Processors, via a dedicated memory. In this prior art document, there is no description of a re-synchronization function for merging the result of the coprocessor with the result of another process ran by a main processor: the operation is rather a classical coprocessor mechanism whereby the Net processor waits for the result of the request sent to the coprocessor.
There is thus a need to provide a reliable solution to merge results from parser when the network processor receives packets from the network with results from an external coprocessor to which the parser may have sent a request when parsing a data packet.
It is noted that the embodiments of the invention as described above can apply to any type of external coprocessor such as a processor, an application specific integrated circuit (ASIC) or a field programmable gate array (FPGA) coprocessor.